Method of wire bonding over active area of a semiconductor circuit

ABSTRACT

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

This application is a continuation application of Ser. No. 10/434,142,filed on May 8, 2003, which claims priority to Provisional PatentApplication Ser. No. 60/418,551, filed on Oct. 15, 2002, both of whichare herein incorporated by reference in their entirety.

RELATED PATENT APPLICATIONS

This application is related to (MEG00-003), filed on May 7, 2001, Ser.No. 09/858,528, now issued as U.S. Pat. No. 6,593,649 and to(MEG02-009), filed on May 8, 2003, Ser. No. 10/434524, both assigned(under a joint Assignment) to the Assignee of the instant invention.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices,and more particularly to the fabrication of wire bond pads overunderlying active devices, passive devices and/or weak dielectriclayers.

(2) Background of the Invention

Performance characteristics of semiconductor devices are typicallyimproved by reducing device dimensions, resulting in increased devicedensities and increased device packaging densities. This increase indevice density places increased requirements on the interconnection ofsemiconductor devices, which are addressed by the packaging ofsemiconductor devices. One of the key considerations in the packagedesign is the accessibility of the semiconductor device or theInput/Output (I/O) capability of the package after one or more deviceshave been mounted in the package.

In a typical semiconductor device package, the semiconductor die can bemounted or positioned in the package and can further be connected tointerconnect lines of the substrate by bond wires or solder bumps. Forthis purpose the semiconductor die is provided with pads (bond pads)that are, typically mounted around the perimeter of the die, and arelocated such as not to be formed over regions containing active orpassive devices.

One reason the bond pads are not formed over the active or passivedevices is related to the thermal and/or mechanical stresses that occurduring the wire bonding process. During wirebonding, wires are connectedfrom the bond pads to a supporting circuit board or to other means ofinterconnections.

The semiconductor industry has recently turned increasingly to lowdielectric-constant (or low-k) materials for intermetal dielectrics.However, such materials typically have lower mechanical strength thantraditional insulating materials and are thus also susceptible to damageby wire bonding.

U.S. Pat. No. 4,636,832 (Abe et al.) describes a method of forming abond pad over an active area, using a silicon layer for stressreduction.

U.S. Pat. No. 5,751,065 (Chittipeddi et al.) discloses a method ofproviding an integrated circuit with active devices under the bond pads,and uses metal for stress relief.

U.S. Pat. No. 6,384,486 (Zuniga et al.) shows a method of forming anintegrated circuit under a contact pad, also using a metal layer forstress absorption.

U.S. Pat. No. 6,229,221 (Kloen et al.) describes forming a wire bond toa bond pad formed over active devices, where the bond pad andpassivation must have specified thickness and be substantially free frominterruptions under the wire bonding region.

SUMMARY OF THE INVENTION

A principal objective of the invention is to provide a method andstructure to enable wire bond connections over device regions of asemiconductor die, whereby damage to underlying layers of dielectric,active and/or passive devices is avoided.

Another objective of the invention is to reduce semiconductor die size,and thus manufacturing cost, for integrated circuits to be connected tonext level packaging by wire bonding.

In accordance with the objectives of the invention, a new method andstructure for enabling wire bond connections over active regions of anIntegrated Circuit die is provided. A semiconductor die, on which areformed active and/or passive devices, has at least one interconnectmetal layer having at least one top level metal contact, and apassivation layer over the interconnect metal layer, wherein thepassivation layer comprises at least one opening through which isexposed the top level metal contact point. A compliant metal bond pad isformed over the passivation layer, connected to the top level metalcontact through the opening.

Various types, configurations or designs of openings through the layerof passivation are provided. Optionally, a layer of compliant materialis formed between the compliant metal bond pad and passivation. Wirebonding may later be performed to the bond pad.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 a and 1 b show conventionalmethods of creating wire bond connections to an Integrated Circuit die.

FIG. 2 is a cross-sectional drawing of the invention for a compliantmetal to which a wire bond connection has been made.

FIG. 3 shows a cross section of a second embodiment of the invention forcompliant metal to which a wire bond connection has been made.

FIG. 4 a and 4 b show a cross sections of a third embodiment ofinvention showing compliant metal to which a wire bond connection hasbeen made.

FIGS. 5 a-5 c show cross sections of a fourth embodiment of theinvention, for a compliant material over which a layer of pad metal hasbeen created, a wire bond connection has been made to the layer of padmetal.

FIG. 6 shows a cross section of a fifth embodiment of the invention, fora compliant material over which a layer of pad metal has been created, awire bond connection has been made to the layer of pad metal.

FIG. 7 shows a cross section of compliant metal.

FIGS. 8 a through 8 c show layers of material that can be used to formcompliant metal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Conventional wire bonding methods and methods of I/O interconnect canresult in damage being inflicted on underlying layers of dielectric,such as those layers of dielectric over which the interconnecting bondpads are formed. Furthermore, common industry practice has been tolocate active devices away from the areas under bond pads, to avoiddamage to the devices during wire bonding. This results in a significantincrease in die size, causing extra manufacturing cost.

The invention provides a method which allows wire bonding connections toa semiconductor die to be made over active and/or passive devices,without damage to the devices or to intervening dielectric layers.

Conventional wire bond connections are provided along the periphery ofan Integrated Circuit (IC). The bond pads are laterally displaced fromthe active device region in order to avoid the negative impact ofmechanical stress that is introduced to and through underlying layers ofdielectric during and as a result of wire bonding.

This is illustrated using FIGS. 1 a and 1 b, whereby FIG. 1 a highlightsa first region 70 in which active and/or passive devices are formed. Thefirst region 70 is separate from a second region 75, over which bondpads 77 are formed. The top view shown in FIG. 1 a is shown in crosssection in FIG. 1 b, wherein specifically are highlighted a substrate71, in or over the surface of which active and/or passive devices 72have been created. A first layer 73 of interconnect metal is shown,which is typically connected at one or more points by contacts 74, todevices 72. One or more overlying layers 81 of interconnect metal areformed, in one or more layers of intermetal dielectric 76, with a topmetal layer from which bond pads 77 are formed. Bond pad 77 and wirebond 80 are formed in second region 75, and are laterally separated fromabove the first region 70. As shown in FIGS. 1 a and 1 b, no activeand/or passive devices are formed underlying the bond pad 77.

This requirement, of laterally separating wire bonding pads 77 fromunderlying active and/or passive devices 72 created in or over asemiconductor die, as highlighted in FIGS. 1 a and 1 b, causes the needfor a significant increase in die size since the area 70 is notavailable at the die top surface for wire bond connections.

The invention will now be described in detail using FIGS. 2-8 c.

Referring first specifically to the cross section that is shown in FIG.2, the following elements are shown:

-   -   10, a substrate in or over which active semiconductor devices        have been created (alternately, or in addition to, passive        elements such as metal lines, capacitors, resistors, inductors        and the like)    -   12, a representative sample of the semiconductor devices that        have been created in or over substrate 10; conductive points of        electrical contact to devices 12 (not shown) are provided    -   14, a first layer of interlevel dielectric    -   15, metal interconnections in one or more layers    -   16, intermetal dielectric    -   17, contact pads formed from the top metal layer of interconnect        metal    -   18, a layer of passivation deposited over the layer 16 of        intermetal dielectric and contact pads 17    -   19, openings created through the layer 18 of passivation for        access to contact pads 17    -   20, of significant importance to the invention, a layer of        compliant metal formed over passivation layer 18    -   22, a wire bond connection provided to layer 20 of complaint        metal.

The preferred method for the creation of wire bonding pad 20 comprisesthe following steps:

-   -   1. barrier layer sputtering    -   2. seed layer sputtering    -   3. a photo-lithographic process to define an opening for the        bulk metal    -   4. electroplating the bulk metal    -   5. photoresist strip    -   6. seed layer metal etch    -   7. barrier layer metal etch.

The barrier layer is formed to a preferred thickness of about 3000Angstroms, and is preferably formed of TiW (titanium tungsten). The seedlayer is formed to a preferred thickness of about 1000 Angstroms and ispreferably Au (gold). The photoresist used in step 3. above ispreferably formed to a thickness of between about 10 and 12 μm.

Compliant metal 20 is preferred to be created to a minimum thickness ofabout 1.0 μm, but is preferably more than 2 μm thick, and is preferablyformed of Au. More generally, the thickness of the compliant metalshould be based on the amount of energy the pad needs to absorb duringwirebonding. The thicker the compliant metal pad thickness, the moreenergy the pad will be able to absorb.

The small passivation openings 19 in FIGS. 2 and 3, have a minimum crosssection of about 0.1 μm, but are preferably at least 0.5 μm. Passivationopenings 19 may be formed over only one of the contact pads 17, butpreferably some or all contact pads 17 under wirebond pad 20 havepassivation openings formed thereover, as shown in FIG. 2.

Referring now to FIG. 3, in an alternative embodiment the wire bondingregion, to which wire bond 22 attaches, is displaced laterally withrespect to one or more of the openings 19 that has been provided throughthe passivation layer 18. This allows for an offset of the wire bond 22with respect to the passivation openings, providing additionalflexibility in positioning the wire bond connection.

With reference to FIG. 4 a, another embodiment is shown providingadditional flexibility of providing wire bond connections to asemiconductor device, by providing a larger contact pad 17. By creatinga large opening 19″ through the passivation layer 18, the layer 20″ ofcompliant metal contacts the top layer 17 of metal over a larger surfacearea, thus decreasing the interconnect series resistance of the bondpad/contact pad connection.

The large passivation opening to contact pad 17, shown in FIG. 4 a, hasa width of between about 40 μm and 100 μm.

Yet another embodiment of the invention is shown in FIG. 4 b, in which alarge contact pad 17 is used, but with multiple openings through thepassivation layer 18, which results in improved planarity of the topsurface of bond pad 20.

In order to further enhance absorption of bonding stresses, theinvention provides for, in another alternative embodiment as shown inFIG. 5 a, a layer 24 of a compliant post-passivation dielectricmaterial, under compliant metal 26. This compliant buffer layer 24 ispreferably an organic material such as polyimide, benzocyclobutene (BCB)or the like, and further assists in preventing damage to underlyingdielectric layer(s) 16 and active/passive devices 12. Other polymermaterials that may be used for layer 24 include elastomers such assilicone, or parylene. Compliant layer 24 is typically deposited byspin-on techniques.

Opening 23 is created through the compliant post-passivation dielectric24, and extends to passivation opening 19, providing access to top levelcontact point 17. The opening may have substantially vertical sidewalls25, however the sidewalls are preferably sloped as shown in FIG. 5 a.Compliant post-passivation dielectric 24, such as polyimide, is spun onand exposed and developed to have vertical sidewalls, however thesubsequent curing process causes the sidewalls to have the desiredslope.

The sidewall slope 25 may have an angle α of 45 degrees or more, and istypically between about 50 and 60 degrees. It may be possible to formthe sidewalls with an angle as small as 20 degrees.

As described earlier, the preferred method for the creation of bond pad26 is electroplating. Processing conditions applied for the embodimentof FIG. 5 a are as follows:

-   -   1. barrier layer metal sputtering    -   2. seed metal sputtering    -   3. photo-lithographic process    -   4. electroplating    -   5. photoresist strip    -   6. seed metal etching, and    -   7. barrier metal etching.

Layer 26 is created to a preferred minimum thickness of about 1 μwithgold the preferred material.

The preferred method for the creation of the compliant buffer layer 24of dielectric is spin coating, with layer 24 preferably created to aminimum thickness of about 2 μm. The preferred deposition processingsteps for the creation of the buffer layer 24 are the following:

-   -   1. spin-coating of photo-sensitive material    -   2. photo lithographic exposure and development, and    -   3. curing.

Alternately, compliant buffer layer 24 may be formed by screen printing,as is known in the art, a layer of polymer, such as polyimide or BCB,and then curing the layer.

FIG. 5 b shows an alternative to the FIG. 5 a structure, in whichmultiple openings in the compliant dielectric layer 24 are formed, toconnect wirebond pad 26 through multiple passivation openings 19 tomultiple contact pads 17.

FIG. 5 c shows another alternative to the FIG. 5 a structure, in whichmultiple openings in the compliant dielectric layer 24 are formed, toconnect wirebond pad 26 through multiple passivation openings 19 to asingle, large contact pad 17.

As yet a further extension, as shown in FIG. 6, the invention providesfor offsetting the location of the wire bond 28 connection with respectto the connection(s) to contact pad(s) 17.

It is clear that the invention lends itself to numerous variations inthe application of the layer of compliant metal and compliantpost-passivation dielectric material. The examples shown using FIGS. 2through 6 have shown only two layers of overlying interconnect traces.It is clear that the invention is not limited to two layers ofinterconnect metal but can be equally applied with any number of suchlayers.

As noted earlier, the invention is not limited to one opening createdthrough a protective layer of passivation. The invention is also notlimited as to the location of the one or more openings that are createdthrough the layer of passivation. What is critical to the invention isthe application of a layer of compliant material, which serves as abuffer between active and/or passive devices and contact pads to whichwire bond connections are to be provided.

Specifically and relating to the above comments it can be realized that,in the cross section shown in FIG. 3, the off-set of the wire bond 22can be provided laterally in either direction with respect to thecontact point 17. Also and still specifically referring to the crosssection of FIG. 3, the opening 19 through the layer 18 of passivationcan be extended to two or more openings, each of the openings providingaccess to points 17 of top level metal over the surface of the layer 16of intermetal dielectric.

The cross sections that are shown in FIGS. 2 and 3 apply to the creationof small contact pads (compared to conventional bond pads) for whichsmall vias are created through the layer 18 of passivation, while thecross section that is shown in FIG. 4 applies to the creation of a largecontact pad for which a large via is created through the passivationlayer 18.

An experiment was performed in which the structure depicted in FIG. 2was formed, using 4 μm thick electroplated gold as the compliant metal20, and Fluorinated Silicate Glass (FSG) as the intermetal dielectric16. After wire bonding, no damage to the intermetal dielectric wasobserved.

Referring now to FIGS. 7 and 8 a-8 c, additional detail will bediscussed with regard to materials and methods of forming the wirebondpad of the invention.

Passivation layer 18 is typically formed of an inorganic material.Typically, this comprises silicon oxide at about 0.5 μm thick over whichis formed silicon nitride at about 0.7 μm thick. Other materials andthicknesses, as are known in the art, may be used. The passivation layerprotects underlying active and/or passive devices from the penetrationof mobile ions, transition metals, moisture, and other contamination.

In one embodiment of the invention, as shown in FIG. 7, a glue/barrierlayer 29 is deposited over passivation layer 18. The glue/barrier layer29 preferably comprises Ti, Cr (chromium), TiW or TiN (titaniumnitride). The preferred method for the creation of glue/barrier layer 29is sputtering.

An electroplating seed layer 30 is formed over the glue/barrier layer29, preferably by sputtering Au to a thickness of about 1000 Angstroms.

Bondpad layer 32, of electroplated soft Au, is formed over the seedlayer, using a photolithographic process as earlier described.

The Au bondpad layer 32, shown in FIG. 7, has the followingcharacteristics:

-   -   a hardness range of less than about 150 Hv (Vickers Hardness),        whereby softer Au is preferred, since softer Au is better suited        for stress absorption during wire bond formation    -   an Au purity larger than about 97%, and    -   a thickness larger than about 1 μm, since a thickness less than        about 1 μm does not provide adequate stress absorption.

Referring now to FIGS. 8 a through 8 c, three further embodiments of theinvention are shown, in which a composite metal system is used to formthe compliant metal pad.

In all three embodiments, a glue/barrier layer 29 is deposited overpassivation layer 18. Layer 29 preferably comprises Ti or Cr, formed toa preferable thickness of about 500 Angstroms. A seed layer 33 is formedover the barrier 29, and preferably comprises sputtered Cu, formed to apreferable thickness of about 5000 Angstroms.

Referring now specifically to FIG. 8 a, a composite metal system34/36/38 is shown, preferably comprising electroplated Cu/Ni/Au,respectively. The bottom layer 34 of Cu forms a bulk conduction layer,and is preferred to have a thickness larger than about 1 μm. Centerlayer 36 of Ni is used as a diffusion barrier, and is preferably formedto a thickness of between about 1 and 5 microns. The top Au layer 38, iswire-bondable, and has a preferred thickness of at least 0.1 micron.Alternately, the top wire bondable layer may be aluminum (Al).

In the next embodiment, as shown in FIG. 8 c, a two-metal system isused. A first bulk conduction layer 34, preferably comprising Cu, isformed over the seed layer 33, and is preferably formed to a thicknessof greater than about 1 micron. The second layer 38, for wire bondingpurposes, is formed over layer 34, and preferably comprises Au of 0.1micron, or Al.

In the embodiment shown in FIG. 8 c, an electroplated solder 40 is usedas the bulk conduction metal, with Au (or Al) layer 38 used forwirebonding. The electroplated solder may comprise Pb-alloy, Sn,Sn-alloy, or a lead-free solder such as AgSn alloy or AgCuSn alloy. Aseed layer 33 preferably comprises Cu or Ni.

In the above embodiments of FIGS. 7 and 8 a-8 c, the compliant metalbond pads are formed as follows. A semiconductor wafer having topcontact pads exposed through a layer of passivation 18 is provided. Theglue/barrier layer 29 and electroplating seed layer 33 are deposited,typically by sputtering. Next, the wafer is coated with a layer ofphotoresist 31 having a thickness of less than 12 microns, with bond padopenings patterned by photolithography, as is known in the semiconductorart. Electroplating is then performed for the various subsequent metallayers shown in these Figures, including the top wire-bondable layer 38of gold. Alternatively, electroless plating may be used to formwire-bondable layer 38 to a thickness of as little as 100 Angstroms. Agold layer 32 with a thickness of less than 12 microns may beelectroplated on the seed layer 30 exposed by the opening in thephotoresist layer 31, as shown in FIG. 7. The photoresist 31 is thenstripped. The seed layer 33 and glue/barrier 29 are etched using thebond pad as a mask, to complete the structure, which is now ready forwire bonding.

For the layers shown in cross section in FIGS. 8 a- 8 c, the Followingpreferred thicknesses apply:

-   -   the layer of Cu 34 is preferred to have a thickness larger than        about 1 μm    -   the diffusion layer 36 of Ni is preferred to have a thickness        larger than about 0.5 μm    -   the wirebondable Au layer 38 is preferred to have a thickness        larger than about 100 Angstroms    -   the layer of Pb-alloy, sn or Sn-alloy 40 is preferred to have a        thickness larger than about 1 μm.    -   Further, with the layer of Pb-alloy, Sn or Sn-alloy, as shown in        the cross section of FIG. 8 c, additional composite layers such        as a layer 34 (of Cu) or a layer 36 (of Ni) can be applied        between layer 40 and the glue/barrier layer 29.    -   To adjust the hardness of the Au layer, the Au layer is annealed        at a temperature of between about 120° C. and 350° C., resulting        in a hardness of between about 150 and 15 HV (the higher        hardness corresponding to a lower annealing temperature, a lower        hardness corresponding to a higher annealing temperature). A        preferred annealing temperature is about 270° C., which results        in a hardness of about 50 Hv. Additionally, annealing may be        performed in an N₂ ambient.

The compliant layer 20, as shown in the cross section of FIG. 1, mayalso be used to form low resistance power and ground planes, and/or forsignal lines, above passivation layer 18, as shown in U.S. Pat. No.6,383,916, which is herein incorporated by reference.

The metal pad of the invention is referred to as “compliant”, as furtherdescribed in the following. The compliant metal pad of the invention canbe used to protect underlying active and/or passive devices and/or low-kdielectrics, from damage during wire bonding, because it serves as botha stress buffer (by its elasticity) and a shock wave absorber (by itsductility). To absorb mechanical energy, a material must be soft,ductile (i.e., malleable), and sufficiently thick. Being soft (i.e.,having high elasticity) is not sufficient to absorb much mechanicalenergy. It is the process of plastic deformation that determines howmuch mechanical energy a material can absorb. Further, the thicker thematerial, the greater is the energy that can be absorbed. Metals such asAu, Cu, solder and Al are all soft, for the purposes of the invention,but Au and solder are able to absorb more mechanical energy than Cu andAl due to their ductility.

The total thickness of the compliant metal bond pads is preferred to bemore than 1.5 um., in order to sufficiently absorb bonding energy.

Low-k dielectric materials that could be used and protected fromwire-bonding damage by the invention include CVD-deposited dielectricsincluding but not limited to polyarylene ether, polyarylene,polybenzoxazole, and spun-on dielectrics having a Si_(w)C_(x)O_(y)H_(z)composition. These low-k dielectrics generally have a dielectricconstant less than 3.0, but are at least less than the dielectriccontant of CVD-deposited SiO₂, which has a dielectric constant of about4.2.

A key advantage of the invention is the reduction in die size allowed bythe placing of bond pads over the active devices, as compared to thetraditional industry practice of laterally displacing the bondingregions from the active region. Further, due to the compliant nature ofgold used in the bond pads of the invention, there are no restrictionson underlying interconnect metal routing.

The compliant metal bond pad of the invention advantageously providesfor absorption of the bonding force during wire bonding, thus preventingdamage to active circuits and/or passive devices located underneath thebond pad. This absorption of the bonding force is otherwise difficult toachieve by, for instance, conventional bond pad materials such asaluminum, which are very difficult to deposit and etch at thicknessessufficient to absorb stress.

The optional, additional organic layer of the invention further helps inabsorbing the force that is exerted during wire bonding.

The invention is particularly beneficial, by providing improved forceabsorption capabilities when compared with prior art methods, fordeep-submicron technologies for which low-k dielectrics (which includesCVD or spun-on materials) are increasingly used.

Although the invention has been described and illustrated with referenceto specific illustrative embodiments thereof, it is not intended thatthe invention be limited to those illustrative embodiments. Thoseskilled in the art will recognize that variations and modifications canbe made without departing from the spirit of the invention. It istherefore intended to include within the invention all such variationsand modifications which fall within the scope of the appended claims andequivalents thereof.

1. A circuit component, comprising: a semiconductor substrate; adielectric layer having a dielectric constant of less than 3.0 over saidsemiconductor substrate; a passivation layer over said dielectric layer;a polymer layer over said passivation layer; a metal pad on said polymerlayer and over said dielectric layer; and a wire bonded to said metalpad.
 2. The circuit component of claim 1, wherein said metal padcomprises a first gold layer and a second gold layer on said first goldlayer.
 3. The circuit component of claim 1, wherein said metal padcomprises a gold layer.
 4. The circuit component of claim 1, whereinsaid metal pad comprises a titanium-containing layer, and a gold layeron said titanium-containing layer.
 5. The circuit component of claim 1,wherein said metal pad comprises a gold layer having a thickness ofgreater than 1 m.
 6. The circuit component of claim 1, wherein saidmetal pad comprises a first copper layer and a second copper layer onsaid first copper layer.
 7. The circuit component of claim 1, whereinsaid metal pad comprises a copper layer, a nickel layer on said copperlayer, and a gold layer on said nickel layer.
 8. The circuit componentof claim 1, wherein said metal pad comprises a copper layer with athickness of greater than 1 m.
 9. The circuit component of claim 1,wherein said metal pad comprises a copper layer, and a gold layer oversaid copper layer.
 10. The circuit component of claim 1, wherein saidmetal pad comprises a copper layer.
 11. The circuit component of claim1, wherein said polymer layer comprises polyimide.
 12. The circuitcomponent of claim 1, wherein said polymer layer comprisesbenzocyclobutene (BCB).
 13. The circuit component of claim 1, whereinsaid passivation layer comprises silicon nitride.
 14. The circuitcomponent of claim 1, wherein said passivation layer comprises nitride.15. The circuit component of claim 1, wherein said passivation layercomprises silicon oxide and silicon nitride.
 16. A circuit component,comprising: a semiconductor substrate; a dielectric layer having adielectric constant of less than 3.0 over said semiconductor substrate;a first metal pad over said dielectric layer; a passivation layer oversaid dielectric layer, an opening in said passivation layer exposingsaid first metal pad; a second metal pad over said dielectric layer,wherein said second metal pad is connected to said first metal padthrough said opening, and wherein said second metal pad comprises afirst gold layer; and a wire bonded to said second metal pad.
 17. Thecircuit component of claim 16, wherein said second metal pad furthercomprises a second gold layer under said first gold layer.
 18. Thecircuit component of claim 16, wherein said second metal pad furthercomprises a titanium-containing layer under said first gold layer. 19.The circuit component of claim 16, wherein said first gold layer has athickness of greater than 1 m.
 20. The circuit component of claim 16,wherein said second metal pad further comprises a copper layer undersaid first gold layer.
 21. The circuit component of claim 16, whereinsaid second metal pad further comprises a copper layer, and a nickellayer on said copper layer, wherein said first gold layer is on saidnickel layer.
 22. The circuit component of claim 16, wherein said secondmetal pad further comprises a copper layer with a thickness of greaterthan 1 m under said first gold layer.
 23. The circuit component of claim16, wherein said passivation layer comprises silicon nitride.
 24. Thecircuit component of claim 16, wherein said passivation layer comprisesnitride.
 25. The circuit component of claim 16, wherein said passivationlayer comprises silicon oxide and silicon nitride.
 26. The circuitcomponent of claim 16, wherein said second metal pad is over said firstmetal pad.
 27. A circuit component, comprising: a semiconductorsubstrate; a dielectric layer having a dielectric constant of less than3.0 over said semiconductor substrate; a passivation layer over saiddielectric layer; a metal pad over said passivation layer, wherein saidmetal pad comprises a first gold layer; and a wire bonded to said metalpad.
 28. The circuit component of claim 27, wherein said metal padfurther comprises a second gold layer under said first gold layer. 29.The circuit component of claim 27, wherein said metal pad furthercomprises a titanium-containing layer under said first gold layer. 30.The circuit component of claim 27, wherein said first gold layer has athickness of greater than 1 m.
 31. The circuit component of claim 27,wherein said metal pad further comprises a copper layer under said firstgold layer.
 32. The circuit component of claim 27, wherein said metalpad further comprises a copper layer, and a nickel layer on said copperlayer, wherein said first gold layer is on said nickel layer.
 33. Thecircuit component of claim 27, wherein said second metal pad furthercomprises a copper layer with a thickness of greater than 1 m under saidfirst gold layer.
 34. The circuit component of claim 27, wherein saidpassivation layer comprises silicon nitride.
 35. The circuit componentof claim 27, wherein said passivation layer comprises a silicon oxideand a silicon nitride over said silicon oxide.